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zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 1 of 18 member of the family applications ? low voltage, high density systems with intermediate bus architectures (iba) ? point-of-load regulators for high performance dsp, fpga, asic, and microprocessor applications ? desktops, servers, and portable computing ? broadband, networking, optical, and communications systems ? active memory bus terminators benefits ? integrates digital power conversion with intelligent power management ? eliminates the need for external power management components and communication bus ? completely programmable via pin strapping and external r and c ? one part that covers all applications ? reduces board space, system cost and complexity, and time to market features ? rohs lead free and lead-solder-exempt products are available ? wide input voltage range: 3v?14v ? high continuous output current: 7a ? wide programmable output voltage range: 0.5v?5.5v ? active digital current share ? output voltage margining ? overcurrent and overte mperature protections ? overvoltage and undervoltage protections, and power good signal tracking the output voltage setpoint ? programmable power-up delay ? tracking during turn-on and turn-off with guaranteed slew rates ? sequenced and cascaded modes of operation ? single-wire line for frequency synchronization between multiple pols ? programmable interleave ? programmable feedback loop compensation ? enable control with programmable polarity ? flexible fault management and propagation ? start-up into the load pre-biased up to 100% ? full rated current sink ? real time current and temperature measurements, monitoring, and reporting ? small footprint smt package: 12.5x22mm ? low profile of 6.5mm ? compatible with conventional pick-and-place equipment ? wide industrial operat ing temperature range ? ul60950 recognized, csa c22.2 no. 60950-00 certified, and tuv en60950-1:2001 certified description power-one?s point-of-load converters are recommended for use with regulated bus converters in an intermediate bus architecture (iba). the zy1207 is an intelligent, fully programmable step-dow n point-of-load dc-dc module integrating digital power conversion and intelligent po wer management. the zy1207 completely eliminates the need for external components for sequencing, tracking, pr otection, monitoring, and reporting. performance parameters of the zy1207 are programm able by pin strapping and external resistor and capacitor and can be changed by a user at any time during product develop ment and service without a need for a communication bus.
zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 2 of 18 reference documents no-bus tm pol converters. z-1000 series application note z-one ? pol converters. eutectic solder process application note z-one ? pol converters. lead-free process application note 1. ordering information zy 12 07 x y ? zz product family: z-one module series: no-bus pol converter output current: 7a output voltage setpoint accuracy: no suffix ? 1.5% or 35mv, whichever is greater. h 1 ? 1.5% or 20mv, whichever is greater rohs compliance: no suffix - rohs compliant with pb solder exemption 2 g - rohs compliant for all six substances dash packaging option 3 : t1 ? 500pcs t&r t2 ? 100pcs t&r t3 ? 50pcs t&r q1 ? 1pc sample for evaluation only k1 ? 1pc mounted on the evaluation board 4 ______________________________________ 1 contact factory for availability. 2 the solder exemption refers to all the restricted materials exc ept lead in solder. these materials are cadmium (cd), hexavalen t chromium (cr6+), mercury (hg), polybrominated biphenyls (pbb), polybromi nated diphenylethers (pbde), and lead (pb) used anywhere except in solder. 3 packaging option is used only for orde ring and not included in the part number printed on the pol converter label. 4 the evaluation board is available in only one configuration: zy1207-k1. example: zy1207hg-t2 : a 100-peices reel of rohs compliant pol converters with the output voltage setpoint of 1.5% or 20mv, whichever is greater. each pol converter is labeled zy1207hg. 2. absolute maximum ratings stresses in excess of the absolute maximum ratings ma y cause performance degradation, adversely affect long- term reliability, and cause permanent damage to the pol converter. parameter conditions/description min max units operating temperature controller case temperature -40 105 ? c input voltage 250ms transient 15 vdc output current (see output current derating curves) -7 7 adc 3. environmental and mechanical specifications parameter conditions/description min nom max units ambient temperature range -40 85 ? c storage temperature (ts) -55 125 ? c weight 8 grams mtbf calculated per telcordia technologies sr-332 6.24 mhrs peak reflow temperature zy1207 zy1207g 245 220 260 ? c ? c lead plating zy1207 and zy1207g 100% matte tin or 1.5m ag over 1.5m ni moisture sensitivity level zy1207 zy1207g 2 3
zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 3 of 18 4. electrical specifications specifications apply at the input voltage from 3v to 14v, output load from 0 to 7a, ambient temperature from -40c to 85c, output capacitance consisting of 110 ? f ceramic and 220 ? f tantalum, and default performance parameters settings unless otherwise noted. 4.1 input specifications parameter conditions/description min nom max units input voltage (v in ) at v in <4.75v, vldo pin needs to be connected to an external voltage source higher than 4.75v 3 14 vdc input current (at no load) v in ? 4.75v, vldo pin connected to vin 50 madc undervoltage lockout (vldo connected to vin) ramping up ramping down 4.00 3.9 vdc vdc undervoltage lockout (vldo connected to v aux =5v) ramping up ramping down 2.8 2.7 vdc vdc external low voltage supply connect to vldo pin when v in <4.75v 4.75 14 vdc vldo input current current drawn from the external low voltage supply at vldo=5v 50 madc 4.2 output specifications parameter conditions/description min nom max units output current (i out ) v in min to v in max -7 1 7 adc output voltage range (v out ) programmable 2 with a resistor between trim and ref pins default (no resistor) 0.5 0.5 5.5 vdc vdc output voltage setpoint accuracy 3 v in =12v, i out =0.5*i out max , room temperature see ordering information line regulation 3 v in min to v in max 0.2 %v out load regulation 3 0 to i out max 0.2 %v out dynamic regulation peak deviation peak deviation settling time slew rate 1a/ ? 5v v in =3.3v to 10% of peak deviation 75 100 30 mv mv ? s output voltage peak-to-peak ripple and noise bw=20mhz full load v in =5.0v, v out 2.5v v in =5.0v, v out >2.5v v in =12v, v out 2.5v v in =12v, v out >2.5v 15 25 25 40 mv mv mv mv temperature coefficient v in =12v, i out =0.5*i out max 50 ppm/c switching frequency 450 500 550 khz 1 at the negative output current (bus terminator mode) efficienc y of the zy1207 degrades resulting in increased internal power di ssipation. therefore maximum allowable negative current under specific cond itions is 20% lower than the current determined from the derati ng curves shown in paragraph 5.5. 2 zy1207 is a step-down converter, thus the output voltage is always lower than the input voltage as show in figure 1. 3 digital pwm has an inherent quantization uncer tainty of 6.25mv that is not included in the specified static regulation paramet ers.
zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 4 of 18 figure 1. output voltage as a function of input voltage and output current 4.3 protection specifications parameter conditions/description min nom max units output overcurrent protection type non-latching, 130ms period threshold 140 %i out threshold accuracy -25 25 %i ocp.set output overvoltage protection type latching threshold follows the output voltage setpoint 130 1 %v o.set threshold accuracy measured at v o.set =2.5v -2 2 %v ovp.set delay from instant when threshold is exceeded until the turn-off command is generated 6 s output undervoltage protection type non-latching, 130ms period threshold follows the output voltage setpoint 75 %v o.set threshold accuracy measured at v o.set =2.5v -2 2 %v uvp.set delay from instant when threshold is exceeded until the turn-off command is generated 6 s 5.0 4.0 3.0 2.0 1.0 v out [v] 14.0 12.0 10.0 8.0 6.0 2.0 4.0 min load 0.2 a v in [v] 3.0 3.3 5.5 2.5 5.5 4.5 3.5 1.5 0.5 6.25
zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 5 of 18 overtemperature protection type non-latching, 130ms period turn off threshold temperature is increasing 120 ? c turn on threshold temperature is decreasing after module was shut down by otp 110 ? c threshold accuracy -5 5 ? c delay from instant when threshold is exceeded until the turn-off command is generated 6 s power good signal (pgood pin) logic v out is inside the pg window and stable v out is outside of the pg window or ramping up/down high low n/a lower threshold follows the output voltage setpoint 90 %v o.set upper threshold follows the output voltage setpoint 110 %v o.set delay from instant when threshold is exceeded until status of pg signal changes 6 s threshold accuracy measured at v o.set =2.5v -2 2 %v o.set ___________________ 1 minimum ovp threshold is 1.0v 4.4 feature specifications parameter conditions/description min nom max units current share (cs pin) type active, single line maximum number of modules connected in parallel i out min =0 4 current share accuracy i out min 20%*i out nom 20 %i out interleave (im and intl2?intl4 pins) interleave (phase lag) programmable via intl2?intl4 pins in 45 ? steps 0 315 degree sequencing (delay pin) power-up delay programmable by capacitor connected to delay pin 210 ms default: c delay =0 0 ms tracking rising slew rate proportional to sync frequency 0.1 v/ms falling slew rate proportional to sync frequency -0.5 v/ms
zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 6 of 18 enable (en and enp pins) en pin polarity enp pin is pulled low enp pin is open negative (enables the output when en pin is pulled low) positive (enables the output when en pin is open or pulled high) en high threshold 2.3 vdc en low threshold 1.0 vdc open circuit voltage en and enp 3.3 vdc turn-on delay from en pin changing state to v out starting to ramp up 0 ms turn-off delay from en pin changing state to v out reaching 0v 11 ms feedback loop compensation (cca0?cca2 pins) cca=7 (default) recommended v in range 8 12 14 vdc recommended c out /esr range, combination of ceramic+ tantalum 50/5 + 220/40 100/5 + 470/40 400/5 + 2000/20 f/m ? f/m ? cca=6 recommended v in range 8 12 14 vdc recommended c out range, tantalum recommended esr range, tantalum 440 40 880 25 10,000 10 f m ? cca=5 recommended v in range 8 12 14 vdc recommended c out /esr range, ceramic 100/5 220/5 400/5 f/m ? cca=3 or cca=4 recommended v in range 3 5 5.5 vdc recommended c out /esr range, combination of ceramic + tantalum 50/5 + 220/40 100/5 + 470/40 200/5 + 880/40 f/m ? f/m ? cca=2 recommended v in range 3 5 5.5 vdc recommended c out /esr range, tantalum 100/25 440/20 1,000/10 f/m ? cca=1 recommended v in range 3 5 5.5 vdc recommended c out /esr range, ceramic 100/5 220/5 400/5 f/m ? cca=0 recommended v in range 6 11 vdc recommended c out /esr range, combination of ceramic+ tantalum 50/5 + 220/40 100/5 + 470/40 200/5 + 880/40 f/m ? f/m ? output current monitoring (cs pin) output current monitoring accuracy 20%*i out nom < i out < i out nom v in =12v -20 +20 %i out conversion ratio duty cycle of the negative pulse corresponding to 100% of nominal current 70 % temperature monitoring (temp pin) temperature monitoring accuracy junction temperature of pol controller -5 +5 ? c conversion ratio junction temperature from -40c to 140c 10 mv/ ? c monitoring voltage range corresponds to -40c to 140c junction temperature range 0.2 2 vdc output impedance temp pin 6.4 k ? remote voltage sense (+vs pin) voltage drop compensation between +vs and vout 300 mv
zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 7 of 18 4.5 signal specifications parameter conditions/description min nom max units vdd internal supply voltage 3.15 3.3 3.45 v sync line vil_s low level input voltage -0.5 0.3 x vdd v vih_s high level input voltage 0.75 x vdd vdd + 0.5 v vhyst_s hysteresis of input schmitt trigger 0.25 x vdd 0.45 x vdd v iol_s low level sink current v(sync)=0.5v 14 60 ma ipu_s pull-up current source v(sync)=0v 300 1000 a tr_s maximum allowed rise time 10/90%vdd 300 ns cnode_s added node capacitance 5 10 pf freq_s clock frequency of external sync line 475 525 khz tsynq sync pulse duration 22 28 % of clock cycle t0 data=0 pulse duration 72 78 % of clock cycle inputs: intl2?intl4, cca0 ?cca2, en, enp, im iup_x pull-up current source v(x)=0 25 110 a vil_x low level input voltage -0.5 0.3 x vdd v vih_x high level input voltage 0.7 x vdd vdd+0.5 v vhyst_x hysteresis of input schmitt trigger 0.1 x vdd 0.3 x vdd v rdnl_x external pull down resistance pin forced low 10 kohm power good and ok inputs/outputs iup_pg pull-up current source v(pg)=0 25 110 a iup_ok pull-up current source v(ok)=0 175 725 a vil_x low level input voltage -0.5 0.3 x vdd v vih_x high level input voltage 0.7 x vdd vdd+0.5 v vhyst_x hysteresis of input schmitt trigger 0.1 x vdd 0.3 x vdd v iol_x low level sink current at 0.5v 4 20 ma current share/sense bus iup_cs pull-up current source at v(cs)=0v 0.84 3.10 ma vil_cs low level input voltage -0.5 0.3 x vdd v vih_cs high level input voltage 0.75 x vdd vdd+0.5 v vhyst_cs hysteresis of input schmitt trigger 0.25 x vdd 0.45 x vdd v iol_cs low level sink current v(cs)=0.5v 14 60 ma tr_cs maximum allowed rise time 10/90% vdd 100 ns
zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 8 of 18 5. typical performance characteristics 5.1 efficiency curves 55 60 65 70 75 80 85 90 95 01234567 output current, a efficiency, % vo=0.5v vo=1.2v vo=2.5v figure 2. efficiency vs. load. vin=3.3v 60 65 70 75 80 85 90 95 01234567 output current, a efficiency, % vo=0.5v vo=1.2v vo=2.5v vo=3.3v figure 3. efficiency vs. load. vin=5v 74 76 78 80 82 84 86 88 90 92 94 01234567 output current, a efficiency, % vo=1.2v vo=2.5v vo=3.3v vo=5.0v figure 4. efficiency vs. load. vin=9.6v 70 72 74 76 78 80 82 84 86 88 90 92 01234567 output current, a efficiency, % vo=1.2v vo=2.5v vo=3.3v vo=5.0v figure 5. efficiency vs. load. vin=12v
zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 9 of 18 55 60 65 70 75 80 85 90 95 0.5 1.5 2.5 3.5 4.5 5.5 output voltage, v efficiency, % vin=5v vin=3.3v vin=9.6v vin=12v figure 6. efficiency vs. output voltage, iout=7a 50 55 60 65 70 75 80 85 90 3 4 5 6 7 8 9 1011121314 input voltage, v efficiency, % vo=0.5v vo=1.2v vo=2.5v figure 7. efficiency vs. input voltage. iout=7a 5.2 turn-on characteristics figure 8. tracking turn-on. vin=12v, ch1 ? v1, ch2 ? v2, ch3 ? v3 5.3 turn-off characteristics figure 9. tracking turn-off vin=12v, ch1 ? v1, ch2 ? v2, ch3 ? v3 5.4 transient response the pictures in figure 10 - figure 15 show the deviation of the output voltage in response to the 50- 75-50% step load at 1.0a/ s. in all tests the pol converters had 5x22 f ceramic capacitors and a 220 f tantalum capacitor connected across the output pins. the speed of the transient response was optimized by selecting appropriate cca settings.
zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 10 of 18 figure 10. vin=12v, vout=1v. cca=00 figure 11. vin=12v, vout=2.5v. cca=00 figure 12. vin=12v, vout=5v, cca=00 figure 13. vin=5v, vout=1v. cca=03 figure 14. vin=5v, vout=2.5v. cca=03 figure 15. vin=3.3v, vout=1v. cca=03
zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 11 of 18 5.5 thermal derating curves 3 3.5 4 4.5 5 5.5 6 6.5 7 45 55 65 75 85 ambient temperature, degree c output current, a 0lfm 100lfm 200lfm 400lfm 600lfm figure 16. thermal derating curves. vin=12v, vout=5.0v 3 3.5 4 4.5 5 5.5 6 6.5 7 45 55 65 75 85 ambient temperature, degree c output current, a 0lfm 100lfm 200lfm 400lfm 600lfm figure 17. thermal derating curves. vin=14v, vout=5.0v
zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 12 of 18 6. typical application pol1 22uf 220uf trim vref im intl2 intl3 intl4 cca0 cca1 cca2 enp en cs sync ok pgood delay temp 4.7uf 4.7uf pol4 22uf 220uf trim vref im intl2 intl3 intl4 cca0 cca1 cca2 enp en cs sync ok pgood delay temp 4.7uf 4.7uf pol3 22uf 220uf trim vref im intl2 intl3 intl4 cca0 cca1 cca2 enp en cs sync ok pgood delay temp 4.7uf 4.7uf pol2 22uf 220uf vldo vin +vs vout pgnd trim vref im intl2 intl3 intl4 cca0 cca1 cca2 enp en cs sync ok pgood delay temp 4.7uf 4.7uf 47uf ibv vo1 vo2 vo3 enable pgnd pgnd pgnd pgnd pgnd vout vout vout vout vin vin vin vin +vs vout pgnd pgnd pgnd pgnd pgnd pgnd vout vout vout vout vldo vin vin vin vin vin vldo vin vin vin vin vin vldo vin vin vin vin vin +vs vout pgnd pgnd pgnd pgnd pgnd pgnd vout vout vout vout +vs vout pgnd pgnd pgnd pgnd pgnd pgnd vout vout vout vout 47uf 47uf 47uf 47uf 47uf 47uf 47uf pgnd pgnd pgnd pgnd figure 18. complete schematic of application with three independent outputs. intermediate bus voltage is from 8v to 14v. in this application four pol converters are configured to deliver three independent output voltages. pol1 and pol2 are connected in parallel for increased output curren t. output voltages are programmed with the resistors connected between trim and vref pins of individual converters. pol1 is configured as a master (im and intl0?intl 4 pins are grounded) and all other pol converters are synchronized to the switching frequency of pol1. in terleave is programmed with pins intl0?intl4 to ensure the lowest input and output noise. pol2 has 180 phase shift, pol 3 and pol4 have phase shifts of 270 and 90 respectively. all converters are controlled by the common enable signal . turn-on and turn-off processes of the system are illustrated by pictures in figure 8 and figure 9.
zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 13 of 18 7. pin assignments and description pin name pin no. pin type buffer type pin description notes vldo 1 p low voltage dropout connect to an external voltage source higher than 4.75v, if v in <4.75v. connect to v in , if v in 4.75v cca0 2 i pu compensation coefficient address bit 0 tie to pgnd for 0 or leave open for 1 cca1 3 i pu compensation coefficient address bit 1 tie to pgnd for 0 or leave open for 1 cca2 4 i pu compensation coefficient address bit 2 tie to pgnd for 0 or leave open for 1 temp 5 a temperature measurement analog voltage proportional to junction temperature of the controller enp 6 i pu enable logic selection tie to pgnd for negative logic or leave open for positive logic intl2 7 i pu interleave bit 2 tie to pgnd for 0 or leave open for 1 intl3 8 i pu interleave bit 3 tie to pgnd for 0 or leave open for 1 intl4 9 i pu interleave bit 4 tie to pgnd for 0 or leave open for 1 cs 10 i/o pu current share/sense connect to cs pin of other z-pols connected in parallel trim 11 a output voltage trim to program the output voltage, connect a resistor between vref and trim pgood 12 i/o pu power good sync 13 i/o pu frequency synchronization line connect to sync pin of other z-pols and/or to an external clock generator ok 14 i/o pu fault status connect to ok pin of other z-1000 pols. leave open, if not used en 15 i pu enable polarity is determined by enp pin vref 16 a voltage reference to program the output voltage, connect a resistor between vref and trim im 17 i pu interleave mode tie to pgnd for master or leave open to set interleave by intl0?intl4 pins delay 18 a power-up delay connect a capacitor between the pin and pgnd to program the power-up delay. leave open for zero delay vout 19- 23 p output voltage +vs 24 i pu positive voltage sense connec t to the positive point close to the load pgnd 25- 31 p power ground vin 32- 36 p input voltage legend: i=input, o=output, i/o=input/output, p=power, a=analog, pu=internal pull-up
zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 14 of 18 8. pin and feature description 8.1 vldo, low voltage dropout the input of the internal linear regulator. v vldo always needs to be greater than 4.75v for normal operation of the pol converter. 8.2 im, interleave mode the input with the internal pull-up resistor. when the pin is left floating, the phase lag of the pol converter is set by intl2?intl4 pins. if the pin is pulled low, the phase lag is set to 0. pulling all intl pins and the im pin low configures a pol converter as a master. the master determines the clock on the sync line. 8.3 temp, temperature measurement the voltage output of the internal temperature sensor measuring junction temperature of the controller ic. voltage range from 0 to 2v corresponds to the temperature range from -50c to 150c. 8.4 enp, enable polarity the input with the internal pull-up resistor. when the enp pin is pulled low, the control logic of the en input is inverted. 8.5 delay, power-up delay the input of the por circuit with the internal pull-up resistor. by connecting a capacitor between the pin and pgnd the power-up delay can be programmed. 8.6 cca[0:2], compensation coefficient address inputs with internal pull-ups to select one of 7 sets of digital filter coefficients optimized for various application conditions. 8.7 vref, voltage reference the output of the 2v internal voltage reference that is used to program the output voltage of the pol converter. 8.8 en, enable the input with the internal pull-up resistor. the pol converter is turned off, when the pin is pulled low (see enp to inverse logic of the enable function). 8.9 ok, fault status the open drain input/output with the internal pull-up resistor. the pol converter pulls its ok pin low, if a fault occurs. pulling low the ok input by an external circuitry turns off the pol converter. 8.10 sync, frequency synchronization line the bidirectional input/output with the internal pull-up resistor. if the pol converter is configured as a master, the sync line propagates clock to other pol converters. if the pol converter is configured as a slave, the internal clock recovery circuit synchronizes the pol conver ter to the clock of the sync line. 8.11 pg, power good the open drain input/output with the internal pull-up resistor. the pin is pulled low by the pol converter, if the output voltage is outside of the window defined by the power good high and low thresholds. note : see the no-bus application note for recommendations on pg deglitching. 8.12 trim, output voltage trim the input of the trim comparator for the output voltage programming. the output voltage can be programmed by a single resistor connected between vref and trim pins. resistance of the trim resistor can be determined from the equation below: , ) 5 . 5 ( 20 out out trim v v r ? ? ? kohms where v out is the desired output voltage in volts. if the r trim is open or the trim pin is shorted to pgnd, the v out =0.5v. 8.13 cs, current share/sense bus the open drain digital input/output with the internal pull-up resistor. the duty cycle of the digital signal is proportional to the output current of the pol converter. external capacitive loading of the pin shall be avoided. 8.14 intl[2:4], interleave bits inputs with internal pull-up resistors. the encoded number determines the phase lag of the pol converter when the im pin is left floating. the phase lag is equal to the number multiplied by 45.
zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 15 of 18 8.15 +vs the positive voltage input of the pol converter feedback loop. 9. application information 9.1 output voltage margining margining can be implemented either by changing the trim voltage as described in the previous paragraph or by changing the resistance between the ref and trim pins. figure 19. margining configuration in the schematic shown in figure 19, the nominal output voltage is set with the trim resistor r trim calculated from the equation in the paragraph 8.12. resistors r up and r down are added to margin the output voltage up and down respectively and determined from the equations below. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? % % 5 20 20 v v r r r r trim trim trim up , k ? ?? ? ? ? ? ? ? ? ? ? ? ? ? % 100 % 20 v v r r trim down , k ? where r trim is the value of the trim resistor in k ? and v% is the absolute value of desired margining expressed in percents of t he nominal output voltage. during normal operation the resistors are removed from the circuit by the switches. the ?margining down? switch is normally closed shorting the resistor r down while the ?margining up? switch is normally open disconnecting the resistor r up . an alternative configuration of the margining circuit is shown in figure 20. in this configuration both switches are normally open that may be advantageous in some implementations. figure 20. alternative margining configuration r up and r down for this configuration are determined from the following equations: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? % % 5 20 20 v v r r r r trim trim trim up , k ? ? ? ? ? ? ? ? ? ? ? ? ? ? % % 100 20 20 v v r r r trim trim down , k ? caution : noise injected into the trim node may affect accuracy of the output voltage and stability of the pol converter. always minimize the pcb trace length from the trim pin to external components to avoid noise pickup. refer to no-bus tm pol converters. z-1000 series application note on www.power-one.com for more application information on this and other product features. ref trim pol pgnd r down r trim margining down switch (normally closed) margining up switch (normally open) r up ref trim pol pgnd r trim r down margining down switch (normally open) margining up switch (normally open) r up
zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 16 of 18 10. mechanical drawings all dimensions are in mm tolerances: 0.5-10 ? 0.1 10-100 ? 0.2 pin coplanarity: 0.1 max figure 21. top (left) and bottom views
zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 17 of 18 figure 22. side view 4 4 0 . 2 0 4 0 . 4 0 . 1 0 7 . 0 2 2 . 8 0 . 1 0 ( b o ) 1 . 1 0 . 3 5 1 . 0 0 figure 23. tape and reel
zy1207 7a no-bus pol data sheet 3v to 14v input ? 0.5v to 5.5v output zd-00697 rev. 1.9, 24-jun-10 www.power-one.com page 18 of 18 22.20 10.40 1.00 12.50 2.60 pin 1 0.60 2.00 118 19 36 (x 36) top view figure 24. recommended pcb pad sizes figure 25. recommended pcb layout for multilayer pcbs notes: 1. nuclear and medical applications - power-one products are not designed, intended for use in, or authorized for use as critic al components in life support systems, equipment used in hazardous envi ronments, or nuclear control systems without the express wr itten consent of the respecti ve divisional president of power-one, inc. 2. technical revisions - the appearance of products, including safety agency certifications pictured on labels, may change depe nding on the date manufactured. specifications are subject to change without notice.

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